vhdl 音频发声（新手，期末作业）

音频发声，但是在芯片上运行蜂鸣器声音不对，有时没声，有时突然就响了。求查看一下代码有啥问题？（完全新手，期末作业）

library ieee ;
    use ieee.std_logic_1164.all ;
    use ieee.numeric_std.all ;

entity sora_world is
  port (
    clock : in std_logic;
    buzzer : buffer std_logic;
    led_lights: out std_logic_vector(7 downto 0)
  ) ;
end entity ; -- sora_world

architecture arch of sora_world is

type DTUNE is array(0 to 7) of integer;
--signal buzz:std_logic;
signal frequence:integer:=47801;
signal beat_clk:std_logic;
constant tunes:DTUNE := (0,47801,42589,37936,35816,31887,28409,25303);

begin
    -- 单位节拍脉冲发生器 --> beat_clk
    beat : process( clock )
    variable counter:integer:=0;
    begin
        if rising_edge(clock) then
            if counter=24999999 then
                counter := 0;
                beat_clk <= not beat_clk;
            else
                counter := counter + 1;
            end if ;
        end if ;
    end process ; -- beat
    -- 音符发声器  --> buzz
    tune : process( clock , frequence)
    variable counter:integer:=0;
    begin
        if rising_edge(clock) then
            if counter=frequence then
                counter := 0;
                buzzer <= not buzzer;
            else
                counter := counter + 1;
            end if ;
        end if ;
    end process ; -- tune

    -- 乐曲谱曲发生器
    song : process( beat_clk )
    variable i:integer range 0 to 7;
    begin
        if rising_edge(beat_clk) then
            if i=7 then
                frequence <= tunes(i);
                led_lights <= "00000000";
                led_lights(i) <= '1';
                i:=0;
            else
                frequence <= tunes(i);
                led_lights <= "00000000";
                led_lights(i) <= '1';
                i:=i+1;
            end if ;
        end if;
    end process ; -- song

end architecture ; -- arch